-- TITLE: ----------------------------------------------------------------- -- testbench for the ALU:(upper hierarchy level 1) -- ----------------------------------------------------------------- -- Description: Crappy quick tester code -- -- -- ----------------------------------------------------------------- -- Course: Computer Architecture Project #2 -- ----------------------------------------------------------------- -- Date | Begin: 12.05.2001 -- -- | End : 12.05.2001 -- ----------------------------------------------------------------- -- Additional Comments: -- -- -- ----------------------------------------------------------------- -- ACCESSING DESIGN LIBRARIES and PACKAGES: ------------------------------------------- ---Library Clause: (Makes the written libraries visible to the design unit) library ieee,work; ----work is working(design) library (there can be only 1!!) use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------ --ENTITY DECLARATION and PORT MAP: (Interface of design unit to external env.) ---------------------------------- entity ALU64_tb is -- ALU64_tb: name of entity -- entity name must be unique in the design library!! -- NO PORTS end ALU64_tb; ------------------------------------------------------------------------------ --ARCHITECTURE BODY: (Internal details, function of block) -------------------- architecture STRUCT of ALU64_tb is -- INTERNAL SIGNALS--> signal UP : std_logic_vector(63 downto 0); -- UP i/p of ALU signal DOWN : std_logic_vector(63 downto 0); -- DOWN i/p of ALU signal SubOP : std_logic_vector(7 downto 0); -- SubOP portion (7:0) of 32 bit instr. signal ALUfunc : std_logic_vector(5 downto 0); -- comes from controller, BITWIDTH arbitrarily assigned for now!! signal ALUout : std_logic_vector(63 downto 0); -- ALU64 o/p -- COMPONENTS--> COMPONENT ALU64 port (OP1 : in std_logic_vector(63 downto 0); -- UP i/p of ALU OP2 : in std_logic_vector(63 downto 0); -- DOWN i/p of ALU SubOP : in std_logic_vector(7 downto 0); -- SubOP portion (7:0) of 32 bit instr. OPcode : in std_logic_vector(5 downto 0); -- comes from controller, BITWIDTH arbitrarily assigned for now!! ALUout : out std_logic_vector(63 downto 0)); -- ALU64 o/p end component ALU64; COMPONENT ALU64_tester port (UP : out std_logic_vector(63 downto 0); -- UP i/p of ALU DOWN : out std_logic_vector(63 downto 0); -- DOWN i/p of ALU SubOP : out std_logic_vector(7 downto 0); -- SubOP portion (7:0) of 32 bit instr. ALUfunc : out std_logic_vector(5 downto 0); -- comes from controller, BITWIDTH arbitrarily assigned for now!! ALUout : in std_logic_vector(63 downto 0)); -- ALU64 o/p end component ALU64_tester; -- Synopsis vhdlsim requires these embedded configurations!!! -- pragma synthesis_off FOR ALL : ALU64 USE ENTITY work.ALU64(behav); FOR ALL : ALU64_tester USE ENTITY work.ALU64_tester(testbench); -- pragma synthesis_on begin -- of architecture alu_1 : ALU64 port map (UP,DOWN,SubOP,ALUfunc,ALUout); tester: ALU64_tester port map (UP,DOWN,SubOP,ALUfunc,ALUout); end STRUCT; --EOArchitecture