My broader research area is related to computer architecture. The context my work spans is Power and Thermal Modeling/Measurement of processors and application power phase behavior analysis. Most of my work is based on real-system analyses. Below are some of the previous projects we completed. Most recent stuff is not updated. I'm hoping for a major renovation soon, before March 2006 hopefully. As a quick snapshot, currently i am working on two projects: (i) Global power management for CMP systems. This is joint with Alper Buyuktosunoglu, Pradip Bose and Chen-Yong Cher. (ii) Runtime phase prediction and phase based power optimizations with Qiang Wu and Prof Doug Clark.

• I have developed a thermal model for a Pentium Pro processor based on Russ Joseph's power modeling project CASTLE. [2002] < Click for details >
  
• I implemented a small and portable LKM and user interface to program and access P4 event counters, which we name PerformanceReader. After this, I have also made a Profiler that has all the setup for periodic counter sampling. [2003] < Click for details >
  
• To be able to measure real processor power consumption, we have built a Real Power Measurement Setup with measurement hardware and monitoring software. [2003] < Click for details >
  
• I have (FINALLY) developed a complete framework that models 22 physical component powers for a P4 (Willamette) processor using performance counter data collected at runtime with the help of Performance Reader and that measures real time processor power for verification. [2003] < Click for details >
  
• Following these, we have done some initial research related to program power phase behavior. Our analyses showed we can extract significant power behavior information from component power data and can identify power phases in application traces, within arbitrarily long timescales. [2003] < Click for details >
  
• We did new research involving the extension of the power phase behavior research. We (11/9/2003) worked on generalizing the phase behavior and grouping ideas to several benchmarks and applications. Then, we investigated to verify the repeatibility of the experiments so that the power behavior is stable and phase analysis is reliable. There are several aspects of the work that 'we have already are still' dealing with such as the mapping of timing information to other architectures to be able to power simulate, PC sampler LKM for collecting basic block info for comparison, a perf. counter based only approach, other statistics, PCA, etc.
  
• Some of these above had been done, and there has been some IBM work too, I'll update them sometime. We managed to reclaim phases under real-system variability, suggested a use based on durations of phases and performed a thorough discussion of phase behavior for power with both basic blocks and power vectors using dynamic instrumentation via Pin. Each of these need to be detailed here!
  
• Currently, I am working on a phase prediction work with application to DVFS on a Pentium M. It involves instruction based tracking and memory related phases. Also I have been writing um some of the IBM work related to dynamic power management for CMP systems with power budget constraints
  
• I had also worked on a detailed real time P4 thermal model. I did some progress, but never concluded the research. Will have to solve my problems with the materials and packaging first, when I restart.