My research lies broadly in the area of computer systems and architecture with an emphasis on architectural and real-system techniques for power-efficient computing systems. My research interests span computer architecture and its interaction with systems software; architectural and real-system techniques for power-efficient, reliable and secure computing systems; hardware performance monitoring; microprocessor power/thermal modeling and real measurement techniques; phase analysis; live, runtime monitoring and prediction of workload phase behavior and phase-driven power and thermal management. One of the primary governing themes in our research is the emphasis we put on bringing real-system experimentation into architecture research and relying on validations with real measurements wherever possible. Below are some brief intros to different aspects of our work under three categories:

  1. Performance Monitoring, Power/Thermal Modeling and Measurement of Microprocessors on Real Systems [2002-2003]
  2. Phase Analysis, Live, Runtime Phase Characterization, Detection and Prediction[2003-2006]
  3. Workload/Phase Adaptive Dynamic Power Management[2004-2007]

1. Performance Monitoring, Power/Thermal Modeling and Measurement of Microprocessors on Real Systems [2002-2003]

  • Runtime Processor Thermal Modeling on Real Systems: We developed a thermal model for a Pentium Pro processor based on Russ Joseph's power modeling project CASTLE. The thermal model is based on a 4-degree Cauer R-C model. Our model uses CASTLE generated component power estimates and computes temperatures in all 4 levels with difference equations. I also worked on a detailed real time P4 thermal model.[2002]
  • Performance Monitoring: We implemented a small and portable LKM (Loadabe Kernel Module) and user interface to program and access Pentium 4 event counters, which we name PerformanceReader. We can modify and track counters with system calls: start, reset, halt, define events, get event counts and set replay MSRs (for replay tagging).[2003]
  • Real Power Measurement: To be able to measure real processor power consumption, we have built a Real Power Measurement Setup with measurement hardware and monitoring software. The power measurement setup consists of a current probe to measure current thru CPU power lines, plugged into a DMM. The DMM sends the data to a logger machine over RS232. The monitoring software we developed: Power Meter & Power Plotter plot the measured power over a sliding timeline of 1000 samples every 100ms. [2003]
  • Live, Runtime Power Monitoring and Estimation on High-End Processors: We developed a complete framework that models 22 physical component powers for a P4 (Willamette) processor using performance counters. The Power Server side collects raw counter information sends it over ethernet to Power Client, which performs component power estimation. Power Client generates the runtime Total Power Monitor that synchronously plots measured and estimated total power. Runtime Component Power Breakdown Monitor tracks per-component powers. With this framework and our empirical power estimations, we can quite accurately estimate unit-wise and total processor power consumption for arbitrarily long application runtimes. [2003][MICRO-36]

2. Phase Analysis, Live, Runtime Phase Characterization, Detection and Prediction [2003-2006]

  • Workload Phase Behavior: Before going into the details of our work in this area, let me first clarify what we mean by application phases. Phases are distinct execution regions of an application that also generally exhibit some level of repetitive behavior due to the procedure and loop-oriented dynamic execution characteristics. The goal of our work is to characterize this phase behavior, with a focus on power, detect the repetitive behavior under system variability and predict future phases.
  • Phase Characterization for Power: We have explored methods to identify dynamically varying power demand, or “power phases” of workloads. Interpreting our derived microarchitecture-level power estimations as characteristic vectors of varying application power behavior, we have shown that similarity analysis methods applied to these characteristic vectors help expose power phase behavior of applications. With this methodology, a small set of (10-20) derived "representative power signatures" characterize overall application power behavior with reasonable accuracy (capturing application power variation within 5% errors). [2003][WWC'03]
  • Comparing Event-Counter-Based and Control-Flow-Based Phase Characterizations: We have also looked at how different representations of application behavior such as our performance features and dynamic execution information (i.e. control flow) perform for accurate phase characterizations. We developed a novel evaluation framework using a combination of dynamic instrumentation with performance monitoring and real power measurements. Our evaluations revealed that while both features provide significant insights to application power behavior, our phase characterizations based on performance events consistently provide a more accurate description of power characteristics, with 40% improvements over control-flow-based approaches. [2005][HPCA-12]
  • Detecting Recurrent Phase Behavior under System Variability: One primary challenge of phase analysis on real systems is identifying repetitive phase patterns under system variability. To extract existing recurrence information despite variability effects, we proposed a "transition-guided" phase detection framework that relies on phase change information to identify repetitive execution. We introduced novel techniques such as “glitch-gradient filtering” and “near-neighbor blurring” to mitigate sampling and variability effects on reflected application phase behavior. This complete detection scheme achieved 2-8X better detection capabilities with respect to value-based phase characterizations, successfully identifying repetitive phase signatures with less than 5% false alarms.[2004][IISWC'05]
  • Runtime Phase Prediction with the Global Phase History Table (GPHT) Predictor: We have considered new methods for projecting future application phase behavior in real-system experiments. Specifically, we proposed a Global Phase History Table (GPHT) predictor that is inspired from an architectural technique, namely global branch history predictor, but implemented in the operating system for runtime phase predictions on real systems. The GPHT predictor significantly improves the accuracy of the predicted behavior, reducing the misprediction rates by 2.4X for applications with varying behavior.[2006][MICRO-39#1]

3. Workload/Phase Adaptive Dynamic Power Management [2004-2007]

  • Phase-Driven Dynamic Power Management on Real Systems: In this study, we used GPHT-based runtime phase predictions to guide dynamic power management. We defined phases classifications that reflect the dynamic voltage and frequency scaling (DVFS) potentials of execution regions. We developed a complete real system prototype that autonomously predicts phases of running applications and adapts processor settings on the fly. These adaptations improved power-performance efficiency of the processor by 27%. [2006][MICRO-39#1]
  • Global Power Management in Chip Multiprocessors: We investigated the trade-offs among different power management strategies for CMPs under varying power budgets. We worked on this project during my 2005 internship at IBM TJ Watson research. This architectural study showed that dynamic per-core management with a global controller can efficiently leverage both inter- and intra-workload variability to significantly improve CMP power-performance efficiency under reduced power budgets. To perform this dynamic management, I have also devised predictive methods to estimate the power/performance of CMP systems across different power modes. Developed global DPM policies performed within 1% power-performance efficiency of an oracle with predictive power mode selections. This per-core management approach achieved 5X and 2X improvements over chip-wide and static approaches, providing consistent responses under varying power budgets and application characteristics.[2005][MICRO-39#2]
  • Power-Efficient Resource Management in Heterogeneous Data Centers: Here, We looked at the applications of DPM strategies at the data center level. This work is done during my internship at Intel Hillsboro/ CTG/ STL/ PCL. This work proposed a power-efficient resource allocation framework guided by an “across-platform workload behavior predictor”. This predictor utilizes architectural application features to project workload behavior on platforms with different architectural and memory system properties. Experiments based on real measurements showed that such power-efficient resource allocation based on across-platform predictions can perform within 2% of an oracular allocator and improves total data center power consumption by 21%.[2006][ICAC-4]

4. Current Work [2007-Onwards]

Right now I have couple projects in the pipeline about considering thermal management with the GPHT environment and going into multithreaded/parallel application management in global CMP power management and considering multiple contexts for phase prediction.





Department of Electrical Engineering
Last Update: Thu, January 4, 2007 19:58